SE98ATP,547【PDF 5/43 页】IC TEMP SENSOR DDR 8-HWSON

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Sheet目录46

1页 2页 3页 4页 [5页]6页 7页 8页 9页

SE98A_4

Product data sheet

Rev. 04 25 November 2009

5 of 43

NXP Semiconductors

SE98A

DDR memory module temp sensor, 1.7 V to 3.6 V

7. Functional description

7.1 Serial bus interface

The SE98A uses the 2-wire serial bus (I

C-bus/SMBus) to communicate with a host

controller. The serial bus consists of a clock (SCL) and data (SDA) signals. The device

can operate on either the I

C-bus Standard/Fast mode or SMBus. The I

C-bus

Standard-mode is defined to have bus speeds from 0 Hz to 100 kHz, I

C-bus Fast-mode

from 0 Hz to 400 kHz, and the SMBus is from 10 kHz to 100 kHz. The host or bus master

generates the SCL signal, and the SE98A uses the SCL signal to receive or send data on

the SDA line. Data transfer is serial, bidirectional, and is one bit at a time with the Most

Significant Bit (MSB) transferred first, and a complete I

C-bus data is 1 byte. Since SCL

and SDA are open-drain, pull-up resistors must be installed on these pins.

7.2 Slave address

The SE98A uses a 4-bit fixed and 3-bit programmable (A0, A1 and A2) 7-bit slave address

that allows a total of eight devices to coexist on the same bus. The input of each pin is

sampled at the start of each I

C-bus/SMBus access. The A0, A1 and A2 pins are pulled

LOW internally. The A0 pin is also overvoltage tolerant, supporting 10 V software write

protection when applied to the SPD that shares common address lines.

Fig 5. Slave address

R/W

002aab304

fixed

hardware

selectable

slave address

MSB

LSB

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